Multi-layer diodes and method of producing same

ABSTRACT

It is proposed to implement the emitter short-circuit structure of a multilayer diode by providing grooves which cut through topmost layer  2  of the multilayer diode. A metal layer  20  applied thereon electrically shorts the topmost layer to subjacent layer  3.

FIELD OF THE INVENTION

The present invention relates to a method for producing multilayerdiodes and thyristors, respectively.

BACKGROUND INFORMATION

From the book “Power Semiconductor Devices” by B. Jayant Baliga, 1995,ISBN Number 0-534-94098-6, PWS Publishing Company, page 266, thyristorshaving an emitter short-circuit structure are described in which thetopmost highly n-doped layer of the multilayer arrangement is restrictedby photolithography to defined regions on the surface.

SUMMARY OF THE INVENTION

In contrast, the method of the present invention has the advantage ofproviding an emitter short-circuit structure which can be produced in asimple manner and in parallel with notches for separating the diodes orthyristors from the wafer used. In addition, because of their lateralextension over the entire silicon wafer, the diffused layers exhibithigh homogeneity, a high yield thereby being attained when manufacturingindividual diodes and thyristors, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a silicon wafer.

FIG. 2 shows a silicon wafer with notches.

FIG. 3 shows a silicon wafer immediately prior to being diced intoindividual chips.

DETAILED DESCRIPTION

FIG. 1 shows the side view of one part of a silicon wafer 1 having adiameter of 125 millimeters and a thickness of 200 micrometers. It showsa layer arrangement 2, 3, 4, 5. Prior to introducing the layerarrangement, the (unprocessed) wafer had a phosphorus doping ofapproximately 2.5×10¹⁷ atoms per cubic centimeter. The manufacture ofthe layer arrangement is described in the following.

To produce p-doped layers 5 and 3, a glass layer approximately 2micrometers thick having approximately 3.2 percent by weight of boron isfirst of all deposited on both sides of the unprocessed wafer. Thedeposition is carried out using chemical vapor deposition (“CVD”) ofboron silane under atmospheric pressure (atmospheric pressure CVD,“APCVD”). This coating step is followed by a first diffusion step todrive the boron into the silicon wafer. The diffusion time isapproximately 28 hours at a temperature of approximately 1265 degreesCelsius under oxidizing atmosphere. After this diffusion step, the glasslayers on both wafer sides are removed by dipping into 50 percentagehydrofluoric acid.

In a further step to produce n-doped topmost layer 2, again using APCVD,a glass layer approximately 1.6 micrometers thick which contains 6.5percent by weight of phosphorus is deposited on one side of the waferthat is now designated as the front. Phosphorus silane can be used asgas.

For the further formation of p-doped layer 5, a glass layer 3micrometers thick having 5 percent by weight of boron is applied in afurther step using APCVD on the back of the wafer opposite the front.The dopants applied on the front and back in this and in the previouslydescribed coating step are now driven in in a further diffusion step at1265 degrees Celsius for 15 hours under oxidizing atmosphere. After thisdiffusion step, the glass layers on both wafer sides are again removedby dipping into 50 percentage hydrofluoric acid.

At this point, the silicon wafer is available in the layer sequenceshown in FIG. 1, highly n-doped layer 2 having a thickness of 20micrometers, p-doped layer 3 having a thickness of 45 micrometers, andhighly p-doped layer 5 having a thickness of 50 micrometers. The n-dopedlayer 4 has the doping of the unprocessed wafer utilized.

In a further step, grooves are introduced into layer 2, for example, bysawing with a diamond saw, such that the bottom of the groove in eachcase lies in layer 3, so that layer 2 is completely cut through in theregion of the grooves. FIG. 2 shows a cross-sectional side view ofsilicon wafer 1 with grooves 10 introduced therein. The distance betweenthe parallel grooves is selectively in a range between 2 and 3millimeters, particularly in a range from 2.2 to 2.6 millimeters; thegroove depth is approximately 30 micrometers. In this context, a secondgroup of grooves is arranged at an angle of approximately 90 degreeswith respect to the grooves visible in FIG. 2, so that the front ispartitioned into rectangular, in particular quadratic areas.

In another step, metal layers are deposited by sputtering simultaneouslyon both sides of the wafer, first of all a chromium layer 70 nanometersthick, followed by a nickel-vanadium layer 160 nanometers thick and asilver layer 100 nanometers thick. FIG. 3 shows the silicon wafer withapplied metal layers, the metal layer on the back forming back-sidecontact 21, and the metal layer on the front forming emittershort-circuit contact 20. The emitter short-circuit contact shortstopmost highly n-doped layer 2 to subjacent p-doped layer 3.

In a further step, the wafer is diced by a sawing step, for example,along each second groove or, as shown in FIG. 3, along each thirdgroove, in each case in the middle of the groove along dicing lines 25.If the wafer is diced along each second groove, chips are yielded havingindividual four-layer diodes (thyristor diodes) with chip dimensions ofapproximately 4.5 by 4.5 millimeters.

The chips are subsequently soldered into press-in diode housings, knownper se, and sealed in with epoxy resin. Typical electricalcharacteristics for the four-layer diodes are:

Breakover voltage: 49 to 52 volts,

Breakover current: 0.8 to 1.2 amperes.

Three-layer diodes (transistor diodes) having an n+/n/p/n+ layersequence can also be produced in an analogous manner to four-layerdiodes. The single difference with respect to the manufacturing methoddescribed is that in the coating steps, a glass layer approximately 1.6micrometers thick having 6.5 percent by weight of phosphorus (instead ofboron) is deposited on the back of the wafer. After the second diffusionstep, the thickness of the back, highly n-doped layer is approximately50 micrometers, analogous to aforesaid layer 5. Typical electricalcharacteristics for the three-layer diodes are:

Breakover voltage: 49 to 52 volts,

Breakover current: 0.8 to 1.2 amperes,

Forward voltage: 1.5 to 2.0 volts given a current of 100 amperes in theforward conducting direction.

In alternative specific embodiments, the described method can also becarried out using different steps which likewise lead to the describedlayer arrangements (for example, the layer arrangement 2, 3, 4, 5).Among these are, for example, foil diffusion processes, vapor-phasecoating processes and/or ion implantation methods. Furthermore, theelectrical characteristics of the diodes can be varied by varying thechip dimensions, the depths of the grooves, the groove pattern ofintersecting grooves, the layer thicknesses or the characteristic valuesof the unprocessed wafer. As is apparent from the literature referenceindicated in the introductory part of the Specification, thyristorsdiffer from four-layer diodes essentially due to an additional gateterminal. Thus, with small changes in the manufacturing methoddescribed, it is also possible to produce thyristors which have anemitter short circuit implemented by a groove.

What is claimed is:
 1. A method for producing one of a multilayer diodeand a thyristor including an emitter short-circuit structure, comprisingthe steps of: producing a multilayer arrangement from a semiconductorwafer; sawing grooves in a front of the multilayer arrangement so that atopmost layer of the multilayer arrangement is cut through; applying aback contact on a back of the multilayer arrangement opposite the frontof the multilayer arrangement, and applying an emitter short-circuitcontact on the front so that the topmost layer and a subjacent layer areshort-circuited; and dicing the multilayer arrangement along a part ofthe grooves to produce separated multilayer chips such that in additionto the grooves along which the dicing is carried out, each multilayerchip includes at least one further groove not subject to the dicingstep, wherein the at least one further groove and corresponding emittershort-circuit contact define an emitter short-circuit structure.
 2. Themethod according to claim 1, wherein: the grooves are equidistant. 3.The method according to claim 1, further comprising the step of:arranging two groups of the grooves that intersect at an angle ofapproximately 90 degrees, so that the front is partitioned intorectangular areas.
 4. The method according to claim 3, wherein: therectangular areas correspond to quadratic areas.
 5. The method accordingto claim 3, wherein: the grooves of each group are arranged at adistance of approximately 2.5 mm.
 6. The method according to claim 1,wherein: the topmost layer has a thickness of approximately 20micrometers, the subjacent layer has a thickness of approximately 45micrometers, and the grooves have a depth of approximately 30micrometers.
 7. The method according to claim 1, wherein: the multilayerarrangement is produced in a chemical vapor deposition operation.
 8. Themethod according to claim 7, wherein: the chemical vapor depositionoperation includes an APCVD operation.
 9. The method according to claim1, wherein: the multilayer arrangement is produced in at least one of afoil diffusion operation, a vapor-phase coating operation, and an ionimplantation operation.